With recent developments of integration technology, operational performance of integrated circuits is increasing. For example, in the art of microprocessors, facilities of integrated circuits are advancing. Conventionally, a microprocessor is associated with flip-flops. Flip-flops provide relatively high logic clocking speeds by reducing setup times, hold times and/or clock-to-output times.
FIG. 1 is a diagram showing a delay path in a conventional digital circuit. This delay path may be utilized in a microprocessor including a first register 10, a second register 12, and a combination logic block 11 between the first and second registers 10 and 12. As shown in FIG. 1, the first and second registers 10 and 12 may operate in sync with a clock signal CLK. For convenience of description, the first and second registers 10 and 12 are assumed as being as rising-edge operable flip-flops.
FIG. 2 is an example timing diagram of signals operating in the digital circuit shown in FIG. 1. As shown in FIG. 2, the first register 10 may transfer data to the combination logic block 11 at a first rising edge of the clock signal CLK. Conventionally, there may be a delay 20, referred to as ‘clock-to-output delay’, after the clock signal CLK transitions. The clock-to-output delay 20 refers to a time from a transition of the clock signal CLK until data is output to the register 10. If data is output from the first register 10, the data may be transferred by way of the combination logic block 11 and arrive at an input terminal D2 of the second register 12 in a setup time 22 before the next rising edge of the clock signal CLK. The setup time 22 may be the time necessary for maintaining a stable condition of a data signal input to the second register 12 before a rising edge of the clock signal CLK.
To increase performance of the delay path, a data-to-clock time (e.g., a sum of the clock-to-output delay 20 and the setup time 22) may be reduced. Reducing data-to-clock time may increase propagation time 21 for which data is transferred through the combination logic block 11. By shortening the data-to-output time, a frequency of the clock signal CLK may be increased to improve performance of the digital circuit. A longer delay path provided to the combination logic block 11 may contribute to decreasing the number of pipeline stages required from conventional microprocessors.
Sense amplifier based flip-flops for detecting small signals may be operable at higher frequencies than conventional flip-flops, however, shortening data-to-output delay in sense amplifier based flip-flops is also limited.